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Mismatch in vector store commit behavior under misaligned base address

module: tooldifftest, gsim, XSpdb, Makefiles, scripts, etc.difftest, gsim, XSpdb, Makefiles, scripts, etc.

type: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmed

Status: Open.

#5279 In OpenXiangShan/XiangShan;

· youzi27 opened on Nov 29, 2025

Problem when using vcs to get coverage

type: problem(issue) Problem (while compiling, running, etc.) requiring help(issue) Problem (while compiling, running, etc.) requiring help

Status: Open.

#5204 In OpenXiangShan/XiangShan;

· E1thannn opened on Nov 12, 2025

Error when make emu with <code> EMU_COVERAGE=1</code>

type: problem(issue) Problem (while compiling, running, etc.) requiring help(issue) Problem (while compiling, running, etc.) requiring help

Status: Open.

#5191 In OpenXiangShan/XiangShan;

· ha0lyu opened on Nov 8, 2025

Peripheral port access efficiency

type: problem(issue) Problem (while compiling, running, etc.) requiring help(issue) Problem (while compiling, running, etc.) requiring help

Status: Open.

#5171 In OpenXiangShan/XiangShan;

· dennis-yosi opened on Nov 4, 2025

BUG when load word from illegal address

module: tooldifftest, gsim, XSpdb, Makefiles, scripts, etc.difftest, gsim, XSpdb, Makefiles, scripts, etc.

type: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmed

Status: Open.

#5137 In OpenXiangShan/XiangShan;

· E1thannn opened on Oct 22, 2025

MIG is Invalid Core

type: problem(issue) Problem (while compiling, running, etc.) requiring help(issue) Problem (while compiling, running, etc.) requiring help

Status: Open.

#5119 In OpenXiangShan/XiangShan;

· dfjs19 opened on Oct 15, 2025

[BOT] REFs report different exception causes at 0x80000000

module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been located

type: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmed

Status: Open.

#4982 In OpenXiangShan/XiangShan;

· poemonsense opened on Aug 27, 2025

[BOT] DUT and REFs disagree on s10, mcause, mtval values.

module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been located

type: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmed

Status: Open.

#4981 In OpenXiangShan/XiangShan;

· poemonsense opened on Aug 27, 2025

[BOT] mstatus/sstatus high bits set unexpectedly at exception entry

module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan

module: tooldifftest, gsim, XSpdb, Makefiles, scripts, etc.difftest, gsim, XSpdb, Makefiles, scripts, etc.

type: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmed

Status: Open.

#4980 In OpenXiangShan/XiangShan;

· poemonsense opened on Aug 27, 2025

Multiple build directories

topic: usabilityTo make XiangShan easier to useTo make XiangShan easier to use

type: feature/requested(issue) Feature request to be considered(issue) Feature request to be considered

Status: Open.

#4933 In OpenXiangShan/XiangShan;

· renau opened on Aug 12, 2025

<code>mcause</code> error when load data

topic: funtionalityTo introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bugTo introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug

type: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmed

Status: Open.

#4864 In OpenXiangShan/XiangShan;

· ha0lyu opened on Jul 4, 2025

The PMC counting register is inaccurate

type: question(issue) Question requiring answer(issue) Question requiring answer

Status: Open.

#4794 In OpenXiangShan/XiangShan;

· WeiShen1011 opened on Jun 9, 2025